Interleaving order generator, interleaver, turbo encoder, and turbo decoder

ABSTRACT

An interleaving order generator for a turbo encoder/decoder prevents bottlenecks incurred when temporarily storing a generated interleaving pattern. An interleaving order generator, an interleaver, a turbo encoder, and a turbo decoder realizes a minimum parameter transfer to reduce bottlenecks in the interface, even when the data rate is varied and the interleave length is frequently changed. The interleaving order generator enables a sufficient data transfer rate for providing multi-media services.

BACKGROUND ART

The present invention relates to a prime interleaver used for W-CDMA inthe IMT 2000 (third-generation mobile communication system), and moreparticularly, to an interleaving sequence generator, an interleaver, aturbo encoder, and a turbo decoder, having a reduced memory for theinterleaving sequence generator.

The wideband CDMA (W-CDMA) is standardized as one of radio accessnetworks (RANs) in the third-generation mobile communication system (IMT2000). An internal interleaver for turbo coding, so-called primeinterleaver is standardized. This primer interleaver is disclosed indetail in “3rd Generation Partnership Project; Technical SpecificationGroup Radio Access Network; Multiplexing and channel coding (FDD)(Release 1999) 3G TS25.212 V3.3.0 (2000-06), Section 4.2.3.2.3 “Turbocode internal interleaver” pp. 16–20”.

The turbo encoder comprises a plurality of component encoders. Theinterleaver decorrelation the parity sequences from the componentencoders. The component encoders are concatenated via the interleaver.The interleaver plays an important role in achieving good performance ofturbo coding.

FIG. 15 is a diagram showing an example of the structure of aconventional turbo encoder. Referring to FIG. 15, the turbo encodercomprises a plurality of recursive systematic convolutional encoders1502 and 1503, and an interleaver 1501. The recursive systematicconvolutional encoders 1502 and 1503 comprise an adder and a unit delayelement. An information bit, a parity bit 1, and a parity bit 2 areoutput every bit of information series that is inputted to the turboencoder. The interleaver 1501 is inserted in front of the componentencoder 1503 so as to decrease the correlation between the parity bit 1and the parity bit 2.

FIG. 16 is a diagram showing an example of the structure of aconventional turbo decoder. The turbo decoder comprises two softinput/soft output decoder (also referred to as soft-in/soft-outdecoders, hereinafter, abbreviated to SISOs) 1603 and 1604, twointerleavers 1601 and 1602, and two deinterleavers 1606 and 1607 whichrestores the sequence to its original order. A splitter 1605 splitsparity sequence 1 and 2 into the corresponding SISOs, and a detector1608 detects that the finally-obtained soft output data is subjected tothe hard decision as binary data.

FIG. 17 shows an example of the conventional interleaver for permutingbased on the unit of bit data in the interleaving sequence stored(stored as an interleave pattern table) in a RAM. In data series 1701for interleaving, the data series is permuted in the bit sequence by aRAM 1702 which stores the interleaving sequence based on theinterleaving pattern table, and thus data series 1703 after interleavingis obtained.

As shown by reference numeral 1702, in the relationship between anoutput of the RAM 1702 and the interleaving pattern table, from thepattern table having R blocks with a length p based on a prime p, datais read in accordance with the longitudinal sequence of 0, 8, 4, 12, 2,. . . as shown by an arrow so as to obtain the data series 1703 afterinterleaving.

According to the standard 3G TS 25.212 V3.3.0 (2000-06) of the IMT 2000(W-CDMA), 5075 types of interleaving patterns must be provided with theinterleaving length of 1 to 40 to 5114 bits based on the unit of bit forvarious multi-media service. The pattern table corresponding to theentire interleaving lengths requires the numerous memory capacity andthis it not realistic. The particle “3G TS25.212 V3.3.0 (2000-06) orTurbo code internal interleaver p. 16 to p. 20 in 4.2.3.2.3 section”discloses a scheme for generating the patterns by a predeterminedoperation in accordance with the interleaving lengths, instead ofstoring the entire types of patterns.

In the prime interleaver disclosed in the particle “3rd GenerationPartnership Project; Technical Specification Group Radio Access Network;Multiplexing and channel coding (FDD) (Release 1999) 3G TS 25.212 V3.3.0(2000-06) or V4.0.0 (2000-12) (Section 4.2.3.2.3 “Turbo code internalinterleaver” pp. 16–20)”, when the data length is p based on the prime pand the number of blocks is R, and the base sequence S(j) for intra-rowsequence permutation is obtained as follows by using a characteristic pand a primitive root ν on the finite field (intra-row permutationprocessing).s(j)=[ν·s(j−1)]mod p, j=1,2, . . . (p−2), and s(0)=1 (1)This is shown as Table. Next, R numbers of q(i) relatively prime to anumber (p−1) obtained by subtracting one from the characteristic on thefinite field are obtained. Finally, the sequence of rows is permutedbased on the unit of row (inter-row permutation processing). Theinter-row permutation is executed based on a predetermined pattern T(i).As the interlacing pattern in this case, a lattice pattern forincreasing the free distance of the intra-rows is used.

In the i-th intra-row permutation, the following processing is executed.U _(i)(j)=s([j·r _(i)]mod(p−1)), j=0, 1, 2, . . . , (p−2), and U_(i)(p−1)=0, (2)where, U_(i)(j) indicates the bit position before permutation,corresponding to the output position after the j-th intra-rowpermutation of the i-th row before the permutation, an equation ofrT(i)=q(i) is established, and T(i) is the position of the i-th rowbefore the above-defined permutation.

One example of the data length K=257 will be described. When the numberof rows R in the two-dimensional matrix is 20, the number of columns pexpressed by the prime p is 257/20=12.85. Consequently, the prime p thatis not less than 12.85 and is the closet is 13. When the characteristicis 13, a primitive root ν is 2 on the finite field.

Then, the base sequence S(j) for inter-row permutation is derived byusing the primitive root ν=2 based on the formula (1). If p=13 and ν=2,then,{s(j)}={1, 2, 4, 8, 3, 6, 12, 11, 9, 5, 10, 7, 0}Finally, zero is inserted.

Next, in the above-mentioned example in the case of p=13, R=20 numbersof q(i) relatively prime to the number (p−1) obtained by subtracting onefrom the characteristic on the finite field are obtained. Consequently,the following result is obtained.{q(i)}={1, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61,67, 71, 73, 79}

Finally, based on the above formula (2), the inter-row permutationprocessing is performed with the row as a unit based on thepredetermined pattern. The permutation pattern between the rows isobtained for increasing the free distance in the case of R=20. That is,Par1:{T(i)}={19, 9, 14, 4, 0, 2, 5, 7, 12, 18, 10, 8, 13, 17, 3, 1, 16,6, 15, 11}.

Further, rT(i)=q(i), then,rT(1)=q(1)=1=r19rT(2)=q(2)=7=r9rT(3)=q(3)=11=r14:rT(19)=q(19)=73=r15rT(20)=q(20)=79=r11

The bit position U_(i)(j) is obtained by substituting the above valuesinto the formula (2).

According to the above-mentioned conventional art, the bit positionU_(i)(j) is calculated by software processing such as DSP (digitalsignal processor) or the like. In addition, the resultant data istransferred to the large-scale RAM 1702 shown in FIG. 17 for theinterleaving processing.

Meanwhile, in the turbo decoder, the iterated decoding is performed. Forexample, in the case of decoding the received data of 2 Mbps with 8iterations, the access to the above-mentioned interleaving sequencerequires the fast operation, e.g., tens MHz. In order to respond to therequirement, the pattern generated in accordance with the abovecalculations is temporarily stored in a fast memory, and the memorystructure needs the access having tens MHz.

However, the capacity of the memory (RAM) requires 66,482 bits(=5,114×13 bits), and greatly shares the turbo decoder. Further, it isnecessary to transfer the data to the RAM for interleaving in the turbodecoder which actually performs the processing of the patterns generatedbased on the above calculations and the interface further needs thetransfer of another data. Thus, there is a bottleneck on the interface.

Further, when the variable-rate function is provided, the interleavinglength is frequently changed. In this case, the bottle neck on theinterface further becomes serious and there is a problem that the ratedoes not follow the transfer rate in the multi-media service.

As mentioned above, the internal interleaver in the turbo decoder usedfor the mobile communication system corresponding to various multi-mediaservices needs various interleaving lengths. Therefore, variousinterleaving patterns are necessary and a numerous memory capacity isrequired. Further, the fast data needs to temporarily store theinterleaving pattern in a fast memory and, then, the fast memorycapacity is necessary. This increases the circuit scale. Further, theservice having a variable-rate function has the interface congestion dueto the parameter transfer.

DISCLOSURE OF INVENTION

In consideration of the above-mentioned problems, and it is one objectof the present invention to provide an interleaving sequence generator,an interleaver, a turbo encoder, and a turbo decoder, in which variousinterleaving-lengths and the transfer rates thereof in the multi-mediaservice are realized with the small RAM-capacity for interleaver.Further, it is another object of the present invention to provide means,by which the load for interface is suppressed and which enables theoperation for following the transfer rate in accordance with themulti-media service when the variable-rate function is provided.

According to the first aspect of the present invention, an interleavingsequence generator comprises means which sets R blocks with a datalength p based on a prime p and generates R different integers q0, q1,q2, . . . , qR−1 relatively prime to (p−1), means which calculates theelement on the finite field when a characteristic is the prime p byraising a primitive root ν to the powers of q₀, q₁, q₂, . . . , q_(R−1),thus to generate and store values ν^q₀(mod p), ν^q₁(mod p), ν^q₂(mod p),. . . , ν^q_(R−1)(mod p), means which raises the values ν^q₀, ν^q₁,ν^q₂, . . . , ν^q_(R−1)(mod p) to the power of j on the finite field,thus to generate values (ν^q₀)^j(mod p), (ν^q₁)^j(mod p), (ν^q₂)^j(modp), . . . , (ν^q_(R−1))^j(mod p), means which generates or records ablock permutation pattern that is predetermined for permuting theblocks, and means iterates, when j=1 to (p−2), such an operation thatone is sequentially added to a value obtained by multiplying, by p, anoutput from the means for generating or recording the block permutationpattern in the 0-th permutation and such an operation that the generatedvalues (ν^q0)^j, (ν^q1)^j, (ν^q2)^j, . . . , (ν^qR−1)^j(mod p) aresequentially added to a value obtained by multiplying, by p, an outputfrom the means for generating or recording the block permutation patternin the j-th permutation.

According to the second aspect of the present invention, theinterleaving sequence generator further comprises: means whichsequentially updates the values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . ,(ν^q_(R−1))^j(mod p) by sequentially inputting the generated and storedvalues ν^q₀, ν^q1, ν^q2, . . . , ν^qR−1(mod p) to a fast finite fieldmultiplier in the iteration when j=1 to (p−2).

According to the third aspect of the present invention, in theinterleaving sequence generator the entire values (ν^q0)^j, (ν^q1)^j,(ν^q2)^j, . . . , (ν^qR−1)^j(mod p) are set to zero when j=p−1.

According to the fourth aspect of the present invention, an interleavingsequence generator comprises means which sets R blocks with a datalength (p−1) based on a prime p and generates R different integers q0,q1, q2, . . . , qR−1 relatively prime to (p−1). In the interleavingsequence generator, the element on the finite field is calculated when acharacteristic is the prime p by raising a primitive root ν to thepowers of ₀, q₁, q₂, . . . , q_(R−1), thus to generate and store valuesν^q₀(mod p), ν^q₁(mod p), ν^q₂(mod p), . . . , ν^q_(R−1)(mod p) and thevalues ν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1)(mod p) are raised to thepower of j on the finite field, thus to generate values (ν^q₀)^j(mod p),(ν^q₁)^j(mod p), (ν^q₂)^j(mod p), . . . , (ν^q_(R−1))^j(mod p), a blockpermutation pattern that is predetermined for permuting the blocks isgenerated or recorded, and, when j=1 to (p−2), the iteration isperformed by such an operation that one is sequentially added to a valueobtained by multiplying, by p−1, an output from the means for generatingor recording the block permutation pattern in the 0-th permutation andsuch an operation that the generated values (ν^q₀)^j, (ν^q₁)^j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) are sequentially added to a valueobtained by multiplying, by p−1, an output from the means for generatingor recording the block permutation pattern in the j-th permutation.

According to the fifth aspect of the present invention, in theinterleaving sequence generator, one is subtracted from the value thatis obtained by sequential addition.

According to the sixth aspect of the present invention, the interleavingsequence generator further comprises means for generating and storingthe value (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) inthe iteration when j=1 to (p−2). In the interleaving sequence generator,the generated and stored values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . ,(ν^q_(R−1))^j(mod p) are sequentially updated by sequentially inputting,to a fast finite field multiplier, the values (ν^q₀)^j, (ν^q₁)^j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p).

According to the seventh aspect of the present invention, aninterleaving sequence generator comprises means which sets R blocks witha data length (p+1) based on a prime p and generates R integers q₀, q₁,q₂, . . . , q_(R−1), relatively prime to p−1, and means which calculateselements on the finite field with the characteristic of prime p byraising a primitive root ν to the powers of q₀, q₁, q₂, . . . , q_(R−1),thus to generate and store values ν^q₀, ν^q₁, ν^q₂, . . . ,ν^q_(R−1)(mod p). In the interleaving sequence generator, the valuesν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1)(mod p) are raised to the power of jon the finite field, thus to generate values (ν^q₀)^j, (ν^q₁)^j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p), a block permutation pattern thatis predetermined for permuting the blocks is generated or recorded, andthe iteration is performed when j=1 to (p−2) by such an operation thatone is sequentially added to a value obtained by multiplying, by p+1, anoutput from the means for generating or recording the block permutationpattern in the 0-th permutation and such an operation that the generatedvalues (ν^q₀)^j, (ν^q₁)^j, (ν^q₀)^j, . . . , (ν^q_(R−1))^j(mod p) aresequentially added to a value obtained by multiplying, by p, an outputfrom the means for generating or recording the block permutation patternin the j-th permutation.

According to the eighth aspect of the present invention, theinterleaving sequence generator further comprises means which generatesand stores the values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . ,(ν^q_(R−1))^j(mod p) in the iteration when j=1 to (p−2). In theinterleaving sequence generator, the stored values are sequentiallyinputted to a fast finite field multiplier, thus to sequentially updatethe values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p).

According to the ninth aspect of the present invention, in theinterleaving sequence generator, the entire values (ν^q₀)^j, (ν^q₁)^j,(νq₂)^j, . . . , (ν^q_(R−1))^j(mod p) are set to 0 when j=p−1.

According to the tenth aspect of the present invention, in theinterleaving sequence generator, the entire values (ν^q₀)^j, (ν^q₁)^j,(νq₂)^j, . . . , (ν^q_(R−1))^j(mod p) are set to p when j=p.

According to the eleventh aspect of the present invention, in theinterleaving sequence generator, when an output signal of theinterleaving sequence generator is over an interleaver target range, thesignal is skipped a next signal within the range is used.

According to the twelfth aspect of the present invention, a plurality offast multipliers on the finite field are provided, a plurality of values(ν^q₀)^j, (ν^q₁)^j, (νq₂)^j, . . . , (ν^q_(R−1))^j(mod p) aresimultaneously updated by sharing with the plurality of fast multiplierson the finite field upon updating of the value (ν^q₀)^j, (ν^q₁)^j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) and, when an output of theinterleaving sequence generator is over an interleaver target range, thesignal is skipped a next signal within the range is used to continuouslygenerate the signal.

According to the thirteenth aspect of the present invention, in theinterleaving sequence generator, two fast multipliers on the finitefield are provided, the two fast multipliers are assigned to valuesν^q₀, ν^q₂, ν^q₄, . . . , ν^q2n(mod p) (n is a natural number) as aneven number and values ν^q₁, ν^q₃, ν^q₅, . . . , ν^q2n−1 (mod p) as anodd number that are obtained by splitting the generated and storedvalues ν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1)(mod p), and simultaneouslyupdates in parallel the values (ν^q₀)^j, (ν^q₂)^j, . . . , ν^q2n(mod p)and (ν^q₁)^j, (ν^q₃)^j, . . . , ν^q2n−1(mod p) by the j-th power on thefinite field.

According to the fourteenth aspect of the present invention, in theinterleaver, data are read from a memory by an output of theinterleaving sequence generating circuit referred to as an addresssignal indicating the address of the memory in which the data is stored,thus to permute the data sequence.

According to the fifteenth aspect of the present invention, in theinterleaver, data are written in a memory by an output of theinterleaving sequence generating circuit referred to as an addresssignal indicating the address of the memory in which the data is to bestored, thus to permute the data sequence.

According to the sixteenth aspect of the present invention, in a turboencoder, the interleaver is an internal interleaver in the turboencoder.

According to the seventeenth aspect of the present invention, in a turbodecoder, one of the interleavers (fourteenth aspect & fifteenth aspect)is an internal interleaver in the turbo decoder and the other is aninternal deinterleavers.

According to the eighteenth aspect of the present invention, in a turbodecoder, an output of an interleaving sequence generator is used as anaddress signal for reading a dual-port memory for storing data, and theaddress signal subjected to the delay operation with a predeterminedvalue is used as an address signal for writing, thus simultaneouslyrealizing an internal interleaver and an internal deinterleavers in theturbo decoder.

According to the nineteenth aspect of the present invention, in aninterleaving sequence generating circuit for providing R blocks with adata length p based on a prime p, and obtaining an output positionU_(i)(j) after j-th intra-row permutation of an i-th row before rowpermutation, by using a primitive root ν on the finite field with acharacteristic p, R table are generated, thus to obtain the U_(i)(j).

According to the present invention, in the mobile communication systemcorresponding to various multi-media services, the interleaver using theprime number used for the turbo decoder can respond to variousinterleaving lengths without the increase in circuit scale. Further, inthe interleaving sequence generator, interleaver, turbo encoder, andturbo decoder, a small RAM-capacity for interleaver is realized and theload for the interface is reduced. Thus, even in the multi-mediaservices having a variable-rate function, the transfer rate is easilyfollowed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a generating block of {(ν^q₀)^j (mod p) to(ν^q_(R−1))^j (mod p)} in an interleaving sequence generator accordingto the present invention;

FIG. 2 is a block diagram for generating the interleaving sequence bythe addition of row positions in the interleaving sequence generatoraccording to the present invention;

FIG. 3 is a block diagram for generating the interleaving sequence whenthe number of columns C is p−1 and a permutation pattern is 0 to C−1 asa subtraction result;

FIG. 4 is a block diagram for continuously generating {(ν^q₀)^j (mod p)to (ν^q_(R−1))^j (mod p)} even in the case of providing two fastmultipliers on the finite field and of skipping a signal;

FIG. 5 is a block diagram for generating the interleaving sequence withthe addition of row positions among blocks for continuously generatingthe interleaving sequence even in the case of skipping the signal;

FIG. 6 is a block diagram for skipping the signal over an interleavertarget range among signals indicating the interleaving sequence;

FIG. 7 is a diagram showing a fast multiplier on the finite field;

FIG. 8 is a diagram showing the component for modulo arithmetic;

FIG. 9 is a diagram for explaining the operation of modulo arithmetic;

FIG. 10 is a diagram showing the interleaving processing using thereading operation;

FIG. 11 is a diagram showing the deinterleaving processing using thewriting operation;

FIG. 12 is a diagram for simultaneously the interleaving processingusing the reading operation from a dual-port RAM and the deinterleavingprocessing using the writing operation;

FIG. 13 is a diagram showing a turbo encoder using an interleavingsequence generator according to the present invention;

FIG. 14 is a diagram showing a turbo decoder using the interleavingsequence generator according to the present invention;

FIG. 15 is a diagram showing an example of the structure of aconventional turbo encoder;

FIG. 16 is a diagram showing an example of the structure of aconventional turbo decoder; and

FIG. 17 is a diagram showing an example of the structure of theconventional turbo decoder for permutation based on the unit of bit inaccordance with the interleaving sequence stored in a RAM.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described withreference to the drawings.

FIG. 13 is a block diagram showing a turbo encoder using an interleavingsequence generator according to the present invention. Although theoperation of the turbo encoder shown in FIG. 13 will be described later,mainly, the turbo encoder shown in FIG. 13 is different from aconventional turbo encoder shown in FIG. 15 in an interleaver 1501.

Referring to FIG. 17, the conventional interleaver needs a large-scaleRAM 1702 which stores the interleaving sequence. On the contrary,according to the embodiment, referring to FIG. 13, an interleavingsequence generator 1301 is used to realize a prime interleaver withoutthe large-scale RAM that stores the interleaving sequence.

An interleaving method according to the present invention is basicallysimilar to the above-mentioned prime interleaver. However, according tothe present invention, a position U_(i)(j) is generated in the real timeand the interleaving processing is performed without conventionallypre-calculating the position U_(i)(j) and transferring it to the RAM orthe like. Thus, the large-scale RAM which is conventionally necessary isnot required. Hereinbelow, its method will be described.

First, the following equation is obtained by the formula (1).s(0)=1s(1)=ν mod ps(2)=ν^2 mod p:s(j)=ν^j mod p

Incidentally, a relation of (ν^j)≡ν^(i) is obtained. In the aboveformula, reference symbol ν denotes a primitive root and thus the entireelements on the finite field plane (mod p) are spanned by iterate νmultiplying processing on mod p.

This result is applied to the formula (2) and then the following isobtained.U _(i)(j)=s{[j·r _(i)] mod(p−1)}=[ν^{([j·r _(i)] mod(p−1)}] mod p

Here, in place of [j·r_(i)]mod(p−1)=j·r_(i)−n·(p−1), the following isobtained.U _(i)(j)=[ν^{j·r _(i) −n·(p−1)}]mod p=(ν^r_(i))^j·(ν^(p−1))^(−n) modp={(ν^ r_(i))^ j mod p}·{(ν^(p−1))^(−n) mod p}mod p

Incidentally, based on the Fermat_s Theorem, the following relation isobtained for the whole elements a.a^(p−1)≡1 (mod p), where p: prime

Consequently, the following is obtained.(ν^(p−1))^(−n) mod p=1

Hence, the foregoing formula is as follows.U _(i)(j)=(ν^r _(i))^j mod p(3)

Based on the above description, rT(i)=qi and the following is obtainedbetween the permutation patterns between the rows in the case of R=20.Pat1:{T(0), T(1), . . . , T(R−1)}={19, 9, 14, 4, 0, 2, 5, 7, 12, 18, 10,8, 13, 17, 3, 1, 16, 6, 15, 11}

In this case, the row position T(0) at the 0-th row (j=0) is 19 and q₀(=r19) is selected as a value of the row. Similarly, in the case of thefirst row (i=1), the row position T(1) is 9 and q, (=r9) is selected asa value of the row.

As mentioned above, the row position r_(i) is set to different values.Consequently, the relation (ν^r_(i)) in the formula (3) have variedvalues depending on the rows. The intra-row sequence every row is varieddepending on the rows and becomes random. The value q_(i) given by theequation rT(i)=q_(i) is selected by the relation relatively prime to(p−1). The symbol ν is the primitive root so the order of a is (p−1).

Reference symbol a denotes an arbitrary element in the set defined bymod p. Then, the value p−1 is maximum order in mod p and, hence, thefollowing relation is established.a^(n·(p−1)=(mod p)

Therefore, the condition that the formula (3) is (ν^r_(i))^j=1 (mod p)requires r_(i).j=n·(p−1) and (p−1)|r_(i).j.

On the other hand, the value r_(i) is relatively prime to (p−1) and thevalue r_(i) does not include any factor of (p−1), and this indicates(p−1)|j, namely, the order of (ν^r_(i)) is (p−1) which means the value(ν^r_(i)) is also primitive root under the condition of (mod p).

Therefore, the following relation is obtained.U _(i)(j)=(ν^r_(i))^j mod p, where j=0, 1, 2, . . . , (p−2)

The above relation forms a random-sequence generating algorithm usingthe congruential method as one of the linear congruential methods havinga multiplier of a different primitive root (ν^r_(i)) every row. The(ν^r_(i)) is the primitive root on the prime field and therefore a value(ν^r_(i))^j which is expressed by the power spans the whole element ofthe prime field and it keeps the one-to-one mapping relationship whichneeds interleaver design.

This indicates the acquisition of the value U_(i)(j) without the tablegenerated by the formula (1) of {s(j)=[ν·s(j−1)]mod p, j=1, 2, . . .(p−2), and s(0)=1} by recursively multiplying the value (ν^r_(i)) as amultiplier in the formula (3).

In the case of the data length k=5114 bits, the number of columns pexpressed by the prime number is 5114/20 (=255.7) for 20 as the numberof rows in the two-dimensional matrix and the closest prime number p is257 as the number of columns. As a comparison using the number, thenumber of tables generated by {s(j)=[ν·s(j−1)]mod p, j=1, 2, . . . ,(p−2), and s(0)=1} must be 257. On the contrary, the number of tables is(ν^r_(i)) mod p, (i=0, . . . , 19), namely, 20. The memory capacity isreduced to 1/10 or less.

As will be understood by the foregoing, according to the presentinvention, it is more advantageous as the data length is longer in thecase of the same number of rows. The turbo coding has an interleavergain as a feature and the higher codin-gain is obtained as the datalength is longer. That is, the present invention is preferable to theturbo coding. Although the short data-length is described because of abrief description according to the following embodiment, the data lengthmay have an arbitrary one.

FIG. 1 is a block diagram showing a (ν^q₀)^j (mod p) to (ν^q_(R−1))^j(mod p) generating portion for generating the value U_(i)(j) in theabove formula (3) in the interleaving sequence generator according tothe first embodiment of the present invention. According to the firstembodiment, the data length K is 257 and the two-dimensional matrix isexpressed by the prime p=13 and the number of rows R=20.

At the 0-th row after (ν^r_(i)) permutation used for the foregoing, anequation of (ν^r₁₉)=(ν^q₀) is established. At the first row after thepermutation, an equation of (ν^r₉)=(ν^q₁) is obtained. That is, at therow (i) (=0 to 19), an equation of (ν^rT(i))=(ν^q_(i)) is obtained. Thisindicates that the multiple for the row number i after the permutationmay be (ν^q_(i)).

Here, it is necessary to pay attention to the intra-row relation and therow position before row permutation must be added. In this case, the rowis permuted from T(i) to i and therefore, if the number of columns p=13,then, p×T(i) must be added.

Referring to FIG. 1, a fast multiplier 103 on the finite field isconnected to a register 101 which stores a multiple ν^q₀, ν^q₁, ν^q₂, .. . , ν^q_(R−1) (mod p) via a selector 104. The multiplier outputs areconnected to a register 102 which temporarily stores multiplying resultsvia a selector 105. An output from the register 102 is output via aselector 106 and is further connected to one input terminal of themultiplier 103.

The selectors 104, 105, and 106 are controlled for the interlockingselection and, for the row number i=0 to R−1, the selector 104 selectsν^q₀ (mod p) to ν^q_(R−1) (mod p) and the selectors 105 and 106 select(ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p).

The selector is alternately address-controlled and the register isreplaced with the RAM so as to realize the similar structure.Hereinbelow, a description is given of the operation for generating theinterleaving sequence according to the present invention with referenceto FIG. 1.

First, the operation for the 0-th permutation will be described. Theentire initial values of the register 102 are preset to ‘1’. In thetransition from the 0-th permutation corresponding to J=0 to the firstpermutation corresponding to j=1, the entire selected values of theselector 106 are ‘1’. This value is inputted to one input-terminal ofthe multiplier 103 and is output from an output terminal 107. That is,in the case of the 0-th permutation corresponding to j=0, the entirevalues of the output terminal 107 are ‘1’.

In this case, the selector 104 sequentially selects ν^q₀ (mod p) toν^q_(R−1) (mod p). The output of the multiplier 103 is ν^q₀ (mod p) toν^q_(R−1) (mod p) and the selector 105 interlocking thereto sequentiallyupdates ν^q₀ (mod p) to ν^q_(R−1) (mod p) in the register 102, in placeof the initial value ‘1’.

Next, in the first permutation corresponding to j=1, the selected valueof the selector 106 is ν^q₀ (mod p) to ν^q_(R−1) (mod p). When thisvalue is inputted to the one input-terminal of the multiplier 103, ν^q₀(mod p) to ν^q_(R−1) (mod p) is transmitted from the output terminal107.

Then, the selector 104 sequentially selects ν^q₀ (mod p) to ν^q_(R−1)(mod p) and the output of the multiplier 103 is (ν^q₀)^2 (mod p) to(ν^q_(R−1))^2 (mod p). The selector 105 interlocking operation theretoinputs and sequentially updates, in the register 102, (ν^q₀)^2 (mod p)to (ν^q_(R−1))^2 (mod p) in place of ν^q₀ (mod p) to ν^q_(R−1) (mod p).

The similar operation continues. Then, in the j-th permutation, theselected value of the selector 106 is (ν^q₀)^j (mod p) to (ν^q_(R−1))^j(mod p). This value is inputted to the one input terminal of themultiplier 103 and then (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p) aretransmitted from the output terminal 107. In this case, the selector 104sequentially selects ν^q₀ (mod p) to ν^q_(R−1) (mod p) and the output ofthe multiplier 103 is (ν^q₀)^(j+1) (mod p) to (ν^q_(R−1))^(j+1) (mod p).The selector 105 interlocking operating thereto inputs, to the register102, (ν^q₀)^(j+1) (mod p) to (ν^q_(R−1))^(j+1) (mod p) which aresequentially updated in place of (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (modp).

The above-generated (ν^q₀)^j (mod p) to (ν^q_(R−1))^ j (mod p) arevalues which are read in the column direction of the two-dimensionalmatrix after the intra-row permutation in the formula (3) ofU_(i)(j)=(ν^r_(i))^j mod p.

As mentioned above, the row position before the row permutation needs tobe added. That is, when the row is permuted from T(i) to i, p×T(i) needsto be added.

FIG. 2 is a block diagram showing an interleaving sequence generatoraccording to the first embodiment of the present invention.

Referring to FIG. 2, reference numeral 201 denotes the (ν^q₀)^j (mod p)to (ν^q_(R−1))^j (mod p) generating portion. Reference numeral 205denotes a table which previously stores a block permutation pattern T(i)and T(i) (i=0 to R−1) is output in accordance with the row updating.

A selector 204 selects a (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p)generating portion 201 (where j=0 to p−2). However, finally, when j=p−1,the selector 204 selects a zero output portion 202 for outputting a zerooutput. For the final column, a value of p×T(i) (i=0 to R−1) istransmitted from an output terminal 209 as the interleaving sequenceoutput.

A set value of a column number setting portion 206 for setting thenumber of columns in the two-dimensional matrix is p according to thefirst embodiment. A multiplier 207 generates p×T(i). An adder 208 addsthe value of p×T(i) and the value selected by the selector 204.

The transition timing from a value of (ν^q₀)^j (mod p) when i=0 to avalue of (ν^q_(R−1))^j (mod p) when i=R−1 in the (ν^q₀)^j (mod p) to(ν^q_(R−1))^j (mod p) generating portion 201 is synchronous to thetransition timing for outputting the block permutation pattern T(i) (i=0to R−1) from the table 205. Thus, the output of the adder 208 becomes avalue read in the column direction of the two-dimensional matrix usingU_(i)(j)=(ν^r_(i))^j mod p after the intra-row permutation.

Next, the case of data length K=280 will be described. The row number Rin the two-dimensional matrix is 20. Since 280 divided by 20 equals 14,the closest prime more than 14 should be selected. However, if thecolumn number C=p+1 and the prime p=13, then, the two-dimensional matrixcan be used. Then, the two-dimensional matrix of 14×20 is considered. IfC=p+1, then, the primitive root is similarly used. The primitive root onthe finite field with the characteristic of 13 is 2. A formula forintra-row permutation is shown as follows by using the primitive rootν=2.

The formula for the intra-row permutation is as follows.U _(i)(j)=(ν^r _(i))^j mod p, where j=0, 1, 2, . . . , (p−2)

The above formula is derived because of the above-mentioned reason whenthe column number C=p. Hereinbelow, a description will be given of theinterleaving sequence generator when C=p+1 according to the presentinvention.

Similarly to the case of C=p, (ν^rT(i))=(ν^q_(i)) (i=0 to 19) afterpermutation is obtained. Therefore, the multiple for the row number iafter permutation may be (ν^q_(i)). Since the row is permuted from theT(i) to i, the number of columns C is p+1=13+1=14. Then, a value of(p+1)×T(i) must be added.

The processing is executed by the interleaving sequence generator shownin FIG. 2. Referring to FIG. 2, in the case of C=p+1 similarly to thecase of C=p, the value (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p) (i=0 top−2) generated in FIG. 1 is realized by the same processing. Theselector 204 selects the (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p)generating portion 201 (j=0 to p−2). When j=p−1, the selector 203selects the zero output portion 202. In this case, the multiplier 207multiplies the block permutation pattern T(i) in the table 205 and thevalue of C=p+1 set by the column number setting portion 206. Themultiplying result is output to an output terminal 209 via the adder208.

Finally, when j=p, the selector 204 selects a value of p set by ap-setting portion 203. At the final column, the addition of the value ofp and the value of (p+1)×T(i) where i=0 to R−1 is transmitted from theoutput terminal 209 as the interleaving sequence output. Here, from thetable 205, the block permutation pattern T(i) where i=0 to R−1 is outputin accordance with the row updating.

In this case, the column number setting portion 206 sets a column numberset value in the two-dimensional matrix to p+1, the multiplier 207generates, and the adder 208 adds the value of (p+1)×T(i) and the valueselected by the selector 204.

The transition timing from a value of (ν^q₀)^j (mod p) when i=0 to avalue of (ν^q_(R−1))^j (mod p) when i=R−1 in the (ν^q₀)^j (mod p) to(ν^q_(R−1))^j (mod p) generating portion 201 is synchronous to thetransition timing for outputting the block permutation pattern T(i) (i=0to R−1) from the table 205. Thus, the output of the adder 208 becomesthe value read in the column direction of the two-dimensional matrixusing U_(i)(j)=(ν^r_(i))^j mod p after the intra-row permutation,similarly to the case of C=p.

Next, an example of the data length K=320 will be described. The numberof rows R in the two-dimensional matrix is 20. Since 320/20=16, thecolumn number C is the closest prime p=17. However, if the column numberC=p−1=16, then, the two-dimensional matrix can be used. Then, theapplication of the two-dimensional matrix 16×20 is considered. In thecase of C=p−1, the primitive root is similarly used. The primitive rooton the finite field with the characteristic of 17 is 3.

The formula for intra-row permutation with the primitive root ν=3 is asfollows.U _(i)(j)=(ν^r_(i))^j mod p, where j=0, 1, 2, . . . , (p−2)

The above formula is derived because of the above-mentioned reason inthe case of the column number C=p.

Hereinbelow, a description is given of the case of applying, to thecolumn number C=p−1, the interleaving sequence generator according tothe present invention with reference to FIG. 1. Similarly to the case ofC=p, an equation of (ν^rT(i))=(ν^qi) (i=0 to 19) after permutation isobtained. Therefore, a multiple may be (ν^q_(i)) for the row number iafter permutation. Since the row is permuted from the T(i) to i, thenumber of columns C is (p−1)=17−1=16 and then (p−1)×T(i) must be added.

The interleaving sequence generator shown in FIG. 2 performs theprocessing. Similarly to the case of C=p, in the case of i=0 to p−2,values of (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p) generated in FIG. 1are realized through the same processing with the number of columnsC=p−1. In the case of the number of columns C=p, when i=p−1, a zerooutput portion 202 is selected. However, in the case of the number ofcolumns C=p−1, the row number i equals 0 to p−2. Therefore, the selector204 still selects the (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p)generating portion 201 and selects neither the zero output portion 202nor the p output portion 203. In the case of the number of columnsC=p−1, the zero output portion 202 is not selected and therefore thesequence permutation pattern is 1 to C. Then, one can be subtracted fora value which is generated so that the permutation pattern matches 0 toC−1.

FIG. 3 is a block diagram showing an example of the structure of theinterleaving sequence generator in the case of C=p−1. In the case ofC=p−1, the operation corresponding to the selector 204 is not used.

Outputs from a (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p) generatingblock 301 are directly inputted to an adder 308. The adder 308 receivesa value of (−1) from a constant generating portion 310 which outputs avalue of (−1) for subtraction. A multiplier 307 multiplies the number ofcolumns C=p−1 in the two-dimensional matrix from a column number settingportion 306 to a block permutation pattern T(i) in a table 305. Thisresult (p−1)×T(i) is inputted to the adder 308. These adding results aretransmitted from an output terminal 309 as the interleaving sequenceoutputs.

FIG. 4 is a block diagram showing a (ν^q₀)^j (mod p) to (ν^q_(R−1))^j(mod p) generating block for generating U_(i)(j) in the above formula(3) in the interleaving sequence generator according to the secondembodiment of the present invention.

When the output signal from the interleaving sequence generator is overthe interleaver target range, the signal is skipped. However, accordingto the second embodiment, upon the signal skipping, the above-mentionedtwo fast multipliers on the finite field are provided so as continuouslygenerate the signal.

Referring to FIG. 4, the register 101 for storing the multiple ν^q₀,ν^q₁, ν^q₂, . . . , ν^q_(R−1) (mod p) shown in FIG. 1 is split into tworegisters 401 and 411 and, however, the total capacity is the same asthat shown in FIG. 1. Various splitting methods can be used. Here, adescription is given of an example for splitting the register 101 intothe even register 401 which stores a multiple ν^q₀(mod p), ν^q₂(mod p),ν^q₄(mod p), . . . , ν^q_(2n)(mod p) and the odd register 411 whichstores a multiple ν^q₁(mod p), ν^q₃(mod p), ν^q₅(mod p), . . . , ν^q_(2n−1)(mod p) (where n is a natural number).

Two fast multipliers 403 and 413 are on the finite field and obtain onemultiplier-input from the registers that store the multipliers 401 and411 via selectors 404 and 414. The multiplier outputs are connected toregisters 402 and 403 which temporarily store multiplying results viaselectors 405 and 415.

Outputs from the registers 402 and 412 are output to output terminals407 and 417 via selectors 406 and 416, add are connected to one of inputterminals of the multipliers 403 and 413. The selectors 404 to 406 andthe selectors 414 to 416 are controlled for the interlocking selectionand thus the similar calculation result described with reference to FIG.1 can simultaneously be obtained for the even and odd numbers. That is,(ν^q₀)^j, (ν^q₂)^j, . . . , (mod p) and (ν^q₁)^j, (ν^q₃)^j, . . . , (modp) are simultaneously obtained.

Alternately, the selector may be address-controlled and a dual-port RAMfurther may simultaneously execute the access corresponding to the evennumber and the access corresponding to the odd number. One RAM canexecute the same operation of the two registers.

FIGS. 5 to 6 are block diagrams showing an interleaving sequencegenerator according to the second embodiment of the present invention.

According to the second embodiment, by providing the two split (ν^q₀)^j(mod p) to (ν^q_(R−1))^j (mod p) generating blocks shown in FIG. 4, thesignal over the interleaver target range is skipped. In a block shown inFIG. 5, the addition processing (the number of columns corresponding toFIG. 2× block permutation pattern T(i)) is performed. In a block shownin FIG. 6, the signal over the interleaver target range is skipped.

Referring to FIG. 5, the (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p)generating block is split into a (ν^q₀)^j, (ν^q₂)^j, . . . , (mod p)generating block 501 and a (ν^q₁)^j, (ν^q₃)^j, . . . , (mod p)generating block 511. The basic operation thereof is similar to theoperation of the (ν^q₀)^j (mod p) to (ν^q_(R−1))^j (mod p) generatingblock shown in FIG. 2 and a detailed description is omitted.

The column number setting portion 506 and the block permutation patternT(i) generating portion 505 form a single portion because they areshared for both the even one and the odd one. The adder 508 outputs theinterleaving sequence corresponding to the even number from an evenoutput terminal 509 and an adder 518 outputs the interleaving sequencecorresponding to the odd number from an odd output terminal 519.

In a block shown in FIG. 6, the signal over the interleaver target rangeis skipped among the signals indicating the interleaving sequences.Referring to FIG. 6, an interleaving sequence signal corresponding tothe even number is inputted from a block 602. An interleaving sequencesignal corresponding to the odd number is inputted from a block 601.These interleaving sequence signals are compared with a total number ofbits 607 by comparators 604 and 605, and the interleaving sequencesignal having bits more than the total number of bits 607 is skipped asthe signal over the interleaver target range.

The above-generated interleaving sequence signals within the interleaverrange are permuted to the original sequence by a switch 608, and areinputted to an FIFO 609. When the FIFO is full, the FIFO 609 outputs abuffer-full signal. Although not shown, the buffer-full signal becomes ahalt signal 610 for each block and the operation of the blockstemporarily stops.

The final interleaving sequence output is read from the FIFO 609 and thesignal is output from a terminal 611. Then, the halt signal is reset andthe operation of the blocks restarts. That is, the buffering function ofthe FIFO 609 enables the continuous signal-generation of theinterleaving sequence output 611.

FIG. 7 is a block diagram showing an example of the structure of thefinite field multiplier 103 shown in FIG. 1 and the multipliers 403 and413 on the finite field shown in FIG. 4. According to the secondembodiment, the multiplier on the finite field comprises two portions ofmultiplication 701 and modulo arithmetic 702. The modulo arithmetic 702comprises a comparing and subtracting circuit 801 shown in FIG. 8 whichexecutes calculation 901 shown in FIG. 9.

Referring to FIG. 9, in the calculation 901, when the calculation resultof the multiplier 701 is 1010010110000011 as binary data, the modulo isobtained with p=10010011 as an example. First, the most significant 8bits are used in the comparison and subtraction. This is realized withthe structure of the comparing and subtracting circuit 801. Thecomparison result is determined by the most significant bits MSB and, ifit is p or more, the subtracted value is output. The similar processingis performed by shifting 1 bit and finally the modulo arithmetic resultis obtained.

The interleaving sequence generator is described above according to thesecond embodiment. Next, a description is given of the processing foractually permuting the data sequence by using the interleaving sequencegenerator.

FIG. 10 shows a method for the interleaving processing by permuting thesequence of data stored in a RAM. The interleaving processing isperformed by reading the signal from an interleaving sequence generator1001 as an address signal of a RAM 1002. For example, when the series of0, 8, 4, 12, 2, . . . , 7, and 15 is inputted to a read-address (RD Adr)in the RAM 1002 from the interleaving sequence generator, the 0-th data,the eighth data, . . . of the data stored in the address order is outputfrom the RAM 1002 and the data sequence is permuted.

FIG. 11 shows a method for the deinterleaving processing by the writingoperation. Similarly to the interleaving using the reading operationshown in FIG. 10, the signal from the interleaving sequence generator1101 is inputted as an address in a RAM 1102. Unlike that shown in FIG.10, the address signal is a write-address and the data after thedeinterleaving is stored in the RAM 1102.

For example, the above-mentioned interleaved data is inputted to the RAM1102 in the order of the 0-th data, the eighth data, . . . The sameseries of 0, 8, 4, 12, 2, . . . , 7, and 15 as those shown in FIG. 10are inputted to the write-address (WR Adr) in the RAM 1102 from theinterleaving sequence generator 1101. Consequently, the data series arerestored to the first sequence in the RAM 1102 and the addresses 0, 1,2, . . . are restored in the order of the 0-th data, the first data, thesecond data, . . . and the deinterleaving is executed.

Both the deinterleaving and the interleaving can be exchangeabledepending on the patterns. One is called the interleaving and then theother is called the deinterleaving. On the contrary, one is called thedeinterleaving and then the other is called the interleaving. Asmentioned above, both the interleaving and the deinterleaving can berealized by using the same interleaving sequence generator.

FIG. 12 is a diagram showing the simultaneous realization of theinterleaving and deinterleaving with the above-mentioned relation by oneinterleaving sequence generator 1201. The interleaving and thedeinterleaving are used upon permuting extrinsic information in a turbodecoder as will be described later and the a-prior information (apriori).

Referring to FIG. 12, a dual-port RAM 1202 stores a-priori datacorresponding to a reception symbol in the address order. In theupdating period for the interleaving, the series of 0, 8, 4, 12, 2, . .. , 7, and 15 are inputted from the interleaving sequence generator 1201to a read-address in a RAM 1202 in accordance with the interleavingpattern. In accordance therewith, the 0-th data, the eighth data, . . .are output from the RAM 1202.

The interleaved data is processed by a turbo decoder, which will bedescribed later. Thereafter, the processed data needs the deinterleavingfor returning to the original order. Then, a delay element 1203 isinserted, the time is delayed by the processing time of the turbodecoder, and the deinterleaving processing is performed.

For example, it is assumed that the processed data is inputted to theRAM 1202 in the order of the 0-th data, the eighth data, . . . Thewrite-address signals from the interleaving sequence generator 1201 viathe delay element 1203 are 0, 8, 4, 12, 2 . . . , 7, and 15. In the RAM1202, the addresses 0, 1, 2, . . . are restored in the order of the 0-thdata, the first data, the second data, . . . and the deinterleaving isexecuted.

FIG. 13 is a block diagram showing a turbo encoder comprising aninterleaving sequence generator 1301 and a dual-port RAM 1303 for theinterleaving processing using the interleaving sequence generator 1301according to the second embodiment of the present invention.

Similarly to the conventional turbo encoder shown in FIG. 15, the turboencoder according to the second embodiment comprises two componentencoders 1304 and 1305. The component encoder 1304 receives theinformation sequence which is not subjected to the interleavingprocessing. The component encoder 1305 receives the information sequencewhich is subjected to the interleaving processing.

An output of an up counter 1302 is inputted as the address input RD Adr1of the dual-port RAM 1303 and an output of the interleaving sequencegenerator 1301 is inputted as an address input RD Adr2 of the dual-portRAM 1303. Based on an address input RD Adr1 from the up counter 1302,the read information series in the dual-port RAM 1303 is inputted to thecomponent encoder 1304. Based on the address input RD Adr2 from theinterleaving sequence generator 1301, the read interleaved informationseries in the dual-port RAM 1303 is inputted to the component encoder1305.

FIG. 14 is a block diagram showing a turbo decoder having aninterleaving sequence generator 1402 and dual-port RAMs 1407 and 1406for the interleaving processing and the deinterleaving processing usingthe interleaving sequence generator 1402 according to the thirdembodiment of the present invention.

An up counter 1401 or an interleaving sequence generator 1402 isconnected via a selecting switch 1403 to the read-address in thedual-port RAM 1406 which stores the information series. The iterationprocessing in the turbo decoding has decoding using a parity bit 1corresponding to the non-interleaving processing and decoding using aparity bit 2 corresponding to the interleaving processing. The selectingswitches 1403 and 1404 are switches for switching the decoding, and arecontrolled by a switching signal 1405 for half iteration at the oddtimes or even times.

In the non-interleaving processing, the selecting switch 1403 selectsthe up counter 1401 and the selecting switch 1404 selects the parity bit1.

The up counter 1401 is connected to the read-address of the dual-portRAM 1406 which stores the information sequence and therefore thedual-port RAM 1406 outputs the non-interleaved information sequence.Simultaneously, the up counter 1401 is connected to the read-address ina dual-port RAM 1407 via the switch 1403 and therefore the dual-port RAM1407 outputs the non-interleaved a-priori data.

The two signals are added by an adder 1408, and are inputted to asoft-in soft-out decoder (SISO) 1410. The SISO 1410 comprises aso-called LogMAP or Max-LogMAP which performs MAP decodinglogarithmically. The addition processing of the adder 1408 correspondsto the multiplication in the probability calculation.

The MAP algorithm is executed by the calculation result of the adder1408 and the parity bit 1 selected by the switch 1404 and, based on theresult, the addition value at the same timing of a register 1411 issubtracted by the adder 1412 and is inputted to the dual-port RAM 1407as the next apriori data. The same read-address is inputted to thewrite-address of the dual-port RAM 1407 via a register 1409 at the sametiming and therefore the apriori data is stored at the addresscorresponding to the symbol position of the information series.

Next, in the interleaving processing for half iteration, the selectingswitch 1403 selects the interleaving sequence generator 1402, and theselecting switch 1404 selects the parity bit 2.

The interleaving sequence generator 1402 is connected to theread-address of the dual-port RAM 1406 which stores the informationseries and therefore the dual-port RAM 1406 outputs the interleavedinformation series. Simultaneously, the interleaving sequence generator1402 is connected to the read-address of the dual-port RAM 1407 via theswitch 1403 and, therefore, the dual-port RAM 1407 outputs theinterleaved apriori data.

The adder 1408 adds the two signals and the resultant data is inputtedto the soft-in soft-out decoder (SISO) 1410. The addition processing ofthe adder 1408 corresponds to the multiplying operation in thepossibility calculation.

The MAP algorithm is executed by the calculation result of the adder1408 and the parity bit 2 selected by the switch 1404 and, based on theresult, the addition value at the same timing of the register 1411 issubtracted by the adder 1412 and is inputted to the dual-port RAM 1407as the next apriori data. At the write-address of the dual-port RAM1407, the same read-address is inputted at the same timing via theregister 1409 and therefore the apriori data is stored at the originaladdress position. That is, the data is subjected to the deinterleavingprocessing.

According to the feature of the turbo encoder, the iteration processinggreatly improves the decoding performance. Finally, a detector 1413implements the hard decision and, from an output terminal 1414, thedecoding data is output.

1. An interleaving sequence generator comprising: means which sets Rblocks with a data length p based on a prime p and generates R differentintegers q₀, q₁ q₂, . . . , q_(R−1) relatively prime to (p−1); meanswhich calculates the element on the finite field when a characteristicis the prime p by raising a primitive root ν to the powers of q₀, q₁ q₂,. . . , q_(R−1), thus to generate and store values ν^q₀(mod p), ν^q₁(modp), ν^q₂(mod p), . . . , ν^q_(R−1)(mod p); means which raises the valuesν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1) (mod p) to the power of j on thefinite field, thus to generate values (ν^q₀)^j(mod p), (ν^q₁)^j(mod p),(ν^q₂)^j(mod p), . . . , (ν^q_(R−1))^j(mod p); means which generates orrecords a block permutation pattern that is predetermined for permutingthe blocks; and means iterates, when j=1 to (p−2), such an operationthat one is sequentially added to a value obtained by multiplying, by p,an output from said means for generating or recording the blockpermutation pattern in the 0-th permutation and such an operation thatsaid generated values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . ,(ν^q_(R−1))^j(mod p) are sequentially added to a value obtained bymultiplying, by p, an output from said means for generating or recordingthe block permutation pattern in the j-th permutation.
 2. Theinterleaving sequence generator according to claim 1, furthercomprising: means which sequentially updates said values (ν^q₀)^j,(ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) by sequentiallyinputting said generated and stored values ν^q₀, ν^q₁, ν^₂, . . . ,ν^q_(R−1)(mod p) to a fast multiplier on the finite field in theiteration when j=1 to (p−2).
 3. The interleaving sequence generatoraccording to claim 2, further comprising means which sets, to zero, theentire values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p)when j=p−1.
 4. The interleaving sequence generator according to claim 1,further comprising means which sets, to zero, the entire values(ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) when j=p−1.5. The interleaving sequence generator according to claim 1, furthercomprising: means which skips an output signal from said interleavingsequence generator and uses a next signal within an interleaver targetrange when said output signal is over said range.
 6. The interleavingsequence generator according to claim 1, further comprising: meanshaving a plurality of said multipliers on the finite field, whichsimultaneously updates a plurality of the values (ν^q₀)^j, (ν^q₁)^j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) by sharing with said plurality offast multipliers on the finite field upon updating the values (ν^q₀)^j,(ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p).
 7. The interleavingsequence generator according to claim 6, further comprising: meanshaving two said fast multiplier on the finite field, which assigns saidtwo fast multipliers to values ν^q₀, ν^q₂, ν^q₄, . . . , (mod p) as aneven multiple and values ν^q₁, ν^q₃, ν^q₅, . . . , (mod p) as an oddmultiple that are obtained by splitting said generated and stored valuesν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1)(mod p) and which simultaneouslyupdates in parallel the values (ν^q₀)^j, (ν^q₂)^j, . . . , (mod p) and(ν^q₁)^j, (ν^q₃)^j, . . . , (mod p) by the j-th power on the finitefield.
 8. An interleaver comprising means which sets, to an addresssignal of a memory for storing data, an output of said interleavingsequence generating circuit according to claim 1 and reads the data fromsaid memory by said address signal, thus to permute the data.
 9. A turboencoder, wherein said interleaver according to claim 8 is an internalinterleaver in said turbo encoder.
 10. An interleaver, wherein an outputof said interleaving sequence generating circuit according to claim 1 isset to an address signal of a memory for storing data, and the data iswritten to said memory by said address signal, thus to permute the data.11. A turbo decoder comprising: a first interleaver which sets, to anaddress signal of a memory for storing data, an output of saidinterleaving sequence generating circuit according to claim 1, andpermutes the data by reading the data from said memory by said addresssignal; and a second interleaver which sets, to an address signal of amemory for storing data, an output of said interleaving sequencegenerating circuit according to claim 1, and permutes the data bywriting the data to said memory by said address signal, wherein one ofsaid first and second interleavers is an internal interleaver, and theother is an internal deinterleaver.
 12. A turbo decoder, wherein anoutput of said interleaving sequence generator according to claim 1 isset to a read˜address signal of a dual-port memory for storing data andthe data contents are read, the address signal is delayed by apredetermined value and is set to a write-address signal, and the datacontents are written, thus to simultaneously realize an internalinterleaver and an internal deinterleaver in said turbo decoder.
 13. Aninterleaving sequence generator comprising: means which sets R blockswith a data length (p−1) based on a prime p and generates R differentintegers q₀, q₁, q₂, . . . , q_(R−1) relatively prime to (p−1); meanswhich calculates the element on the finite field when a characteristicis the prime p by raising a primitive root ν to the powers of q₀, q₁,q₂, . . . , q_(R−1), thus to generate and store values ν^q₀(mod p),ν^q₁(mod p), ν^q₂(mod p), . . . , ν^q_(R−1)(mod p); means which raisesthe values ν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1)(mod p) to the power of jon the finite field, thus to generate values (ν^q₀)^j(mod p),(ν^q₁)^j(mod p), (ν^q₂)^j(mod p), . . . , (ν^q_(R−1))^j(mod p); meanswhich generates or records a block permutation pattern that ispredetermined for permuting the blocks; and means iterates, when j=1 to(p−2), such an operation that one is sequentially added to a valueobtained by multiplying, by p−1, an output from said means forgenerating or recording the block permutation pattern in the 0-thpermutation and such an operation that said generated values (ν^q₀)^j,(ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) are sequentially addedto a value obtained by multiplying, by p−1, an output from said meansfor generating or recording said block permutation pattern in the j-thpermutation.
 14. The interleaving sequence generator according to claim13, further comprising: means which subtracts 1 from the value that isobtained by sequential addition.
 15. The interleaving sequence generatoraccording to claim 13, further comprising: means which sequentiallyupdates the generated and stored values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, .. . , (ν^q_(R−1))^j(mod p) by sequentially inputting, to a fastmultiplier on the finite field, the values (ν^q₀)^j, (ν^q₁)^ j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) in the iteration when j=1 to(p−2).
 16. The interleaving sequence generator according to claim 13,further comprising: means which skips an output signal of saidinterleaving sequence generator that is over an interleaver target rangeand uses a next signal within said range when the output signal is oversaid range.
 17. The interleaving sequence generator according to claim13, further comprising: means having a plurality of fast multipliers onthe finite field, which simultaneously updates a plurality of the values(ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) by sharingwith said plurality of fast multipliers on the finite field uponupdating the values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . ,(ν^q_(R−1))^j(mod p).
 18. The interleaving sequence generator accordingto claim 17, further comprising: means having two fast multipliers onthe finite field, which assigns said two fast multipliers to valuesν^q₀, ν^q₂, ν^q₄, . . . , (mod p) as an even multiple and values ν^q₁,ν^q₃, ν^q₅, . . . , (mod p) as an odd multiple that are obtained bysplitting said generated and stored values ν^q₀, ν^q₁, ν^q₂, . . . ,ν^q_(R−1)(mod p), and simultaneously updates in parallel the values(ν^q₀)^j, (ν^q₂)^j, . . . , (mod p) and the values (ν^q₂)^j, (ν^q₃)^j, .. . , (mod p) by raising the values to the power of j on the finitefield.
 19. An interleaver, further comprising: means which sets, to anaddress signal of a memory for storing data, an output of saidinterleaving sequence generating circuit according to claim 13, andpermutes the data by reading the data from said memory by said addresssignal.
 20. A turbo encoder, wherein said interleaver according to claim19 is an internal interleaver in said turbo encoder.
 21. An interleaver,wherein an output of said interleaving sequence generating circuitaccording to claim 13 is set to an address signal of a memory forstoring data and the data is written to said memory by said addresssignal, thus to sequentially permute the data.
 22. A turbo decodercomprising: a first interleaver which sets, to an address signal of amemory for storing data, an output of said interleaving sequencegenerating circuit according to claim 13, and permuting the data byreading the data from said memory by said address signal; and a secondinterleaver which sets, to an address signal of a memory for storingdata, an output of said interleaving sequence generating circuitaccording to claim 13, and permutes the data by writing the data to saidmemory by said address signal, wherein one of said first and secondinterleavers is an internal interleaver, and the other is an internaldeinterleaver.
 23. A turbo decoder, wherein an output of saidinterleaving sequence generator according to claim 13 as data contentsis read as a read˜address signal of a dual-port memory for storing data,said address signal is delayed by a predetermined value, and datacontents of said address signal are written as a write-address signal,thus to simultaneously realize an internal interleaver and an internaldeinterleaver in said turbo decoder.
 24. An interleaving sequencegenerator comprising: means which sets R blocks with a data length (p+1)based on a prime p and generates R integers q₀, q₁, q₂, . . . , q_(R−1)relatively prime to a value (p−1); means which calculates elements onthe finite field with the characteristic of prime p by raising aprimitive root ν to the powers of q₀, q₁, q₂, . . . , q_(R−1), thus togenerate and store values ν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1) (mod p);means which raises the values ν^q₀, ν^q₁, ν^q₂, . . . , ν^q_(R−1) (modp) to the power of j on the finite field, thus to generate values(ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j (mod p); means whichgenerates or records a block permutation pattern that is predeterminedfor permuting the blocks; means which iterates, when j=1 to (p−2), suchan operation that one is sequentially added to a value obtained bymultiplying, by p+1, an output from said means for generating orrecording the block permutation pattern in the 0-th permutation and suchan operation that said generated values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, .. . , (ν^q_(R−1))^j(mod p) are sequentially added to a value obtained bymultiplying, by p, an output from said means for generating or recordingsaid block permutation pattern in the j-th permutation.
 25. Theinterleaving sequence generator according to claim 24, furthercomprising: means which sequentially updates the values (ν^q₀)^j,(ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) by sequentiallyinputting said generated and stored values ν^q₀, ν^q₁, ν^q₂, . . . ,ν^q_(R−1)(mod p) to a multiplier on the finite field in the iterationwhen j=1 to (p−2).
 26. The interleaving sequence generator according toclaim 24, further comprising: means which sets, to 0, the entire values(ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) when j=p−1.27. The interleaving sequence generator according to claim 24, furthercomprising: means which sets, to p, the entire values (ν^q₀)^j,(ν^q₁)^j, (ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p) when j=p.
 28. Theinterleaving sequence generator according to claim 24, furthercomprising: means which skips an output signal of said interleavingsequence generator when it is over an interleaver target range and usesa next signal within said range.
 29. The interleaving sequence generatoraccording to claim 24, further comprising: means having a plurality offast multipliers on the finite field, which simultaneously updates aplurality of values (ν^q₀)^j, (ν^q₁)^j, (ν^q₂)^j, . . . ,(ν^q_(R−1))^j(mod p) by sharing with said plurality of fast multiplierson the finite field upon updating of the values (ν^q₀)^j, (ν^q₁)^j,(ν^q₂)^j, . . . , (ν^q_(R−1))^j(mod p).
 30. The interleaving sequencegenerator according to claim 29, further comprising: means having twofast multipliers on the finite field, which assigns said two fastmultipliers to values ν^q₀, ν^q₂, ν^q₄, . . . , (mod p) as an evennumber and values ν^q₁, ν^q₃, ν^q₅, . . . , (mod p) as an odd numberthat are obtained by splitting the generated and stored values ν^q₀,ν^q₁, ν^q₂, . . . , ν^q_(R−1) (mod p), and simultaneously updates inparallel the values (ν^q₀)^j, (ν^q₂)^j, . . . , (mod p) and (ν^q₁)^j,(ν^q₃)^j, . . . , (mod p) by the j-th power on the finite field.
 31. Aninterleaver comprising: means which sets an output of said interleavingsequence generating circuit according to claim 24 to an address signalof a memory for storing data and reads the data from said memory by saidaddress signal, thus to permute the data sequence.
 32. A turbo encoder,wherein said interleaver according to claim 31 is an internalinterleaver in said turbo encoder.
 33. An interleaver, wherein an outputof said interleaving sequence generating circuit according to claim 24is set to an address signal of a memory for storing data and the data iswritten to said memory by said address signal, thus to sequentiallypermute the data.
 34. A turbo decoder comprising: a first interleaverhaving means which sets, to an address signal of a memory for storingdata, an output of said interleaving sequence generating circuitaccording to claim 24 and reads the data from said memory by saidaddress signal, thus to permute the data; and a second interleaver whichsets, to an address signal of a memory for storing data, an output ofsaid interleaving sequence generating circuit according to claim 24 andwrites the data to said memory by said address signal, thus to permutethe data, wherein one of said first and second interleavers is set to aninternal interleaver and the other is set to an internal deinterleaver.35. A turbo decoder, wherein an output of an interleaving sequencegenerator according to claim 24 containing data contents is read as anaddress signal for reading a dual-port memory for storing data, and theaddress signal subjected to the delay operation with a predeterminedvalue containing the data contents is written as an address signal forwriting, thus simultaneously realizing an internal interleaver and aninternal deinterleavers in said turbo decoder.
 36. A circuit for aninterleaving sequence generator, the circuit comprising: a first memorycomprising R registers that stores and provides a sequence of values,wherein the sequence comprises a primitive root v raised to a power ofan integer q modulo p, wherein p is a prime and each integer q is asequence of different integers q₀, q₁ q₂, . . . , q_(R−1), and eachinteger is relatively prime to (p−1); a second memory comprising Rregisters that sequentially provides a row value stored in theregisters; and a fast multiplier that prompts both the first and secondmemories for values, calculates a product modulo p of the values tocreate a new row permutation value, and stores the new row permutationvalue in the second memory, iteratively R times.
 37. The circuit ofclaim 36, further comprising: a third memory comprising R registers thatsequentially provides a column permutation sequence value; an arithmeticlogic circuit that iteratively p−1 times: calculates a product from acolumn value from the third memory times p; iteratively R times outputsa sequence value calculated from the sum of the product and a rowpermutation value from the second memory; and prompts the fastmultiplier to calculate new row permutation values.